1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. copyright intersil americas inc. 2012. all rights reserved. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. application note 1793 ISL8225MEVAL4Z dual 15a/optional 30a cascadable evaluation board setup procedure the isl8225m is a complete, dual step-down switching mode dc/dc module. the dual outputs can easily be paralleled for single-output, high-current use. it is easy to apply this high-power, current-sharing dc/dc power module to power-hungry datacom, telecom, and fpga applications. all that is needed in order to ha ve a complete, dual 15a design ready for use are the isl8225m, a few passive components, and v out setting resistors. the simplicity of the isl8225m is its off-the-shelf, unassisted implementation. patented current sharing in multi-phase operation greatly reduces rippl e currents, bom costs, and complexity. the isl8225m has a thermally enhanced, compact 17mm x17mm x 7.5mm qfn package that operates at full load and over-temperature without requiring forced-air cooling. easy access to all pins, with few ex ternal components, reduces pcb design to a component layer and a simple ground layer. this ISL8225MEVAL4Z evaluation board is designed for dual 15a output applications. optionally, this board can easily be converted for 30a single output use. multiple ISL8225MEVAL4Z boards can be cascadable through the sync and clkout pins to operate with phase shifting, for paralleling or multiple output us e. the input voltage of this board is 4.5v to 20v and the default outputs on this board are set at 1.2v and 1.5v. related resources recommended equipment ? 0v to 20v power supply with at least 5a source current capability ? electronic load capable of sinking current up to 30a ? digital multimeters (dmms) ? 100mhz quad-trace oscilloscope quick start for dual output operation, th e inputs are ba7 (vin1), ba8 (gnd), ba3 (vin2) and ba4 (gnd). the outputs are ba5 (vout1), ba6 (gnd), ba1 (vout2) and ba2 (gnd). for paralleled single output operation, the inputs are ba7 (vin1) and ba8 (gnd). the outputs are ba5 (vout1) and ba6 (gnd) with ba5 and ba1 shorted. dual output mode 1. connect a power supply capable of sourcing at least 5a to the inputs ba7 (vin1), ba8 (gnd), ba3 (vin2) and ba4 (gnd) of the ISL8225MEVAL4Z evaluation board, with a voltage between 4.5v to 20v. vin1 and vin2 can be different with r18 and r19 open. 2. connect an electronic load or the device to be powered to the outputs ba5 (vout1) and ba6 (gnd), ba1 (vout2) and ba2 (gnd) of the board. all co nnections, especially the low voltage, high current v out lines, should be able to carry the desired load current and should be made as short as possible. see how-to video at intersil.com/ evid03 figure 1. ISL8225MEVAL4Z board image load2 (0a~15a) v out2 4.5v to 20v v in v + - + - v + - load1 (0a~15a) v + - v out1 december 6, 2012 an1793.1
application note 1793 2 an1793.1 december 6, 2012 3. make sure that the setup is connected correctly. turn on the power supply. if the board is working properly, the green led will illuminate; if not, the red led will illuminate (recheck the wire/jumper connections in this case). measure the output voltages, v out1 , which should be at 1.2v and v out2 , which should be at 1.5v 4. if different output voltages are desired, board resistors can be exchanged to provide the desired v out . please refer to table 1 for r2/r4 resistor values, which can be used to produce different output voltages. for 12v v in and v out more than 1.5v, the switching frequency will need to be adjusted, as shown in table 1. the resistor r fset can be adjusted for the desired frequency. no frequency adjustments are necessary for v out below 1.5v. for 5v v in , the frequency does not need to be adjusted and the module default frequency can be used at any allowed v out . if the output voltage is set to more than 1.8v, the output current will need to be derated to allow for safe operation. please refer to the derating curves in the isl8225m datasheet . optional paralleled single output mode 1. to set up the parallel mode, short jp1 (enc), jp2 (vmon) and jp3 (comp) with a jumper. to set up 180 interleaving phase between 2 channels, short the mode pin and gnd pin of jp6 with a jumper. 2. remove r9 and r13. change r14 to 0 ? . change r18 and r19 to 0 ? . short vout1 to vout2 using short wires or copper straps. add c2 for a 470pf capacitor. 3. connect a power supply capable of sourcing at least 5a to the inputs ba7 (vin1), ba8 (gnd), ba3 (vin2) and ba4 (gnd) of the ISL8225MEVAL4Z evaluation board, with a voltage between 4.5v to 20v. vin1 and vin2 need to be shorted together. 4. connect an electronic load or the device to be powered to the outputs ba5 (vout1) and ba6 (gnd) of the board. all connections, especially the low voltage, high current v out lines, should be able to carry the desired load current and should be made as short as possible. 5. make sure the setup is connected correctly prior to applying any power to the board. adjust the power supply to 12v and turn on the input power supply. if the board is working properly, the green led will illuminate; if not, the red led will illuminate (recheck the wire/jumper connections in this case). measure the output voltages, v out1 , which should be at 1.2v. 6. apply any load that is less th an 30a for normal steady state operation. refer to table 1 to change the output voltage by changing resistor r2. optional cascadable mode cascadable mode is needed when multiple evaluation boards are used for paralleling or multiple output use. to demo the parallel features, it is recommended to use isl8225meval2z 6-phase evaluation board for an easy and efficient setup (see an1789 ). otherwise, follow the steps shown below: 1. in order to generate clkout at a shifted phase clock signal, the control loop of vout2 needs to be disabled by connecting vsen2- to vcc. 2. program mode and vsen2+ pin voltages to set the clkout signal and the shifted degrees between two phases on the board (refer to table 3). 3. use a coaxial cable to connect clkout (j5) to sync (j2) of the next evaluation board, which can be programed for parallel or dual output use. 4. if the second board is programed for parallel use, the ishare pins of the first and second boards need to be tied together. using two twisted wires, short two different jumpers of jp7 (ishare/sgnd) on two evaluation boards. add 1nf capacitors of c14 for different boards to decouple the noise. 5. if the third board is used in cascadable mode, the second board can only be used in the parallel mode to generate the clkout signal for the sync pin on the third board. 6. follow the instructions from steps 1 through 5 for more cascadable boards. evaluation board information the evaluation board size is 114.3mm x 76.2mm. it is a 4-layer board, containing 2-ounce copper on the top and bottom layers and 1-ounce copper on all internal layers. the board can be used as a dual 15a reference design. refer to ?layout? on page 6. the board is made of fr4 material and all components, including the solder attachment , are lead-free. thermal considerations and current derating for high current applications, board layout is very critical in order to make the module operate safely and deliver maximum allowable power. to carry large currents, the board layout needs to be designed carefully to maximize thermal performance. to achieve this, select enough trace width, copper weight and the proper connectors. this evaluation board is designed for running dual 15a at room temperature without additional cooling systems needed. table 1. value of bottom resistor (top resistor r1, r3 = 1k ? ) and frequency sele ction for different output voltages v out (v) r2 /r4 ( ) frequency (khz) r fset ( ) (v in = 12v) 1.0 1500 default open 1.2 1000 default open 1.5 665 default open 2.5 316 650 249k 3.3 221 800 124k 5.0 137 950 82.5k 5.5 121 950 82.5k table 2. board configuration for single output 30a application enc vmon mode comp r9 r13 r14 dual open open open open 0 0 open single on on on on open open 0
application note 1793 3 an1793.1 december 6, 2012 however, if the output voltage is increased or the board is operated at elevated temperatures, then the available current is derated. refer to the derated current curves in the datasheet to determine the output current available. for layout of designs using the isl8225m, the thermal performance can be improved by adhering to the following design tips: 1. use the top and bottom layers to carry the large current. vout1, vout2, phase 1, phase 2, pgnd, vin1 and vin2 should have large, solid planes . place enough thermal vias to connect the power planes in different layers under and around the module. 2. phase 1 and phase 2 pads are switching nodes that generate switching noise. keep these pads under the module. for noise-sensitive applications, it is recommended to keep phase pads only on the top and inner layers of the pcb; do not place phase pads exposed to the outside on the bottom layer of the pcb. to improve the thermal performance, the phase pads can be extended in the inner layer, as shown in phase 1 and phase 2 pads on layer 2 (figure 5) for this dual 15a evaluation board. make sure th at layer 1 and layer 3 have the gnd layers to cover the extended areas of phase pads at layer 2 to avoid noise coupling. 3. place the modules evenly on the board and leave enough space between modules. if the board space is limited, try to put the modules with low power loss closely together (i.e. low v out or i out ) while still separating the module with high power loss. 4. if the ambient temperature is high or the board space is limited, airflow is needed to dissipate more heat from the modules. a heat sink can also be applied to the top side of the module to further improve the thermal performance (heat sink recommendation: aavid thermalloy, part number 375424b00034g, www.aavid.com ).
application note 1793 4 an1793.1 december 6, 2012 table 3. isl8225m operation modes 1st module (i = input; o = output; i/o = inpu t and output, bi-direction) modes of operation output (see description for details) operation mode of 2 nd module operation mode of 3 rd module mode en1/ff1 (i) en2/ff2 (i) vsen2- (i) mode (i) vsen2+ (i) clkout/refin wrt 1 st (i or o) vmon2 (note 2) vmon1 of 2 nd module (note 2) 2 nd channel wrt 1 st (o) (note 1) 10 0 - - - --- - --disabled 2a 0 1 active active active - active - vmon1 = vmon2 to keep pgood valid --single phase 2b 1 0 - - - - - - vmon1 = vmon2 to keep pgood valid --single phase 3a 1 1 62% of v cc (i) active - 180 - - dual regulator 41 112) note: 1. ?2 nd channel wrt 1st? means ?second channel with respect to first;? in other words, channel 2 lags channel 1 by the degrees specifi ed in this column. for example, 90 means channel 2 lags channel 1 by 90; -60 means channel 2 leads channel 1 by 60. 2. ?vmon1? means that the pin is tied to the vmon1 pin of the same module. ?divider? means that there is a resistor divider from vout to sgnd; refer to figure 24 in the isl8225m datasheet . ?1k ? ? means that there is a 1k ? resistor connecting the pin to sgnd; refer to figure 22 in the isl8225m datasheet .
application note 1793 5 an1793.1 december 6, 2012 ISL8225MEVAL4Z board schematic figure 2. ISL8225MEVAL4Z board schematic gnd ground and ground are tied together at pin 6 of u1. note: ** ** gnd gnd gnd 22uf 4.12k 1000pf vout2 open tim klemann steven mcgee vin1 ~/isl8225m/ISL8225MEVAL4Zd vmon2 dnp open mode comp2 en/ff1 en/ff2 clkout vmon1 vin1 comp1 pgood isl8225mirz vcc vin2 clkout 330uf 22uf 47uf vcc vout1 vin1 08/04/2011 0 en/ff2 47uf dnp schematic jian yin 1000pf evaluation board 1 1 d pgood vin2 phase2 clkout 3.32k 3.32k 47uf 1000pf 0 isl8225m 4.7uf 4.12k open dnp 16.5k vmon 0 vmon1 enc 330uf open 1k mode vcc open 1000pf open vcc en/ff1 1000pf en/ff1 16.5k phase1 ishare vout1 vout2 ishare open 330uf open 0 open 47uf vin2 en2 665 ssl_lxa3025igc 2n7002-7-f ISL8225MEVAL4Z 10/26/2012 22uf 330uf comp comp1 22uf 1k 1k sync 1000pf 0 open dnp vmon2 comp2 dnp en/ff1 en/ff2 clkout vmon1 ishare comp1 vout2 mode sgnd sync vmon2 comp2 vout1 vcc in in in out in in in out in out in in out in out in in out out out out in vsen2- vsen1- vsen2+ cin1 cin4 1 2 3 6 5 9 4 2 13 15 16 17 18 19 14 8 20 7 1 1 24 2 1 5 1 2 4 2 1 5 phase1 phase2 vsen1+ pgood red grn out ba1 r19 c1 j2 p4 p3 p2 p8 p7 p6 p5 p1 ba8 ba7 ba6 ba5 ba3 j1 j5 j4 c11 r3 jp1 ba4 q1 ba2 rfset r18 released by: drawn by: sheet hrdwr id date: date: date: tester filename: mask# rev. of date: engineer: title: updated by: d e e d e e e e e e e d d d e d d d d d e d d d 1 1 1 12 21 22 24 23 11 10 25 26 21 3 2 1 2 1 2 2 2 1 21 2 3 3 4 3 3 4 43 1 2 pgnd vin1 n/c r15 cin2 r4 r13 c18 jp7 jp6 jp5 jp2 c01 c05 r16 c10 c14 c06 c07 c010 c08 r5 r8 r7 c09 c03 c16 jp4 c5 c04 c21 r6 c02 c4 cin3 jp3 cin5 cin6 c15 c7 c6 c3 c2 pgnd vin2 r20 r22 r21 r14 c9 c8 r12 r9 c12 r11 led1 r1 r10 r2 u1 dnp dnp dnp dnp dnp dnp
application note 1793 6 an1793.1 december 6, 2012 layout figure 3. top silk screen figure 4. top layer component side figure 5. layer 2 figure 6. layer 3
application note 1793 7 an1793.1 december 6, 2012 figure 7. bottom layer solder side figure 8. bottom silk screen layout (continued)
application note 1793 8 an1793.1 december 6, 2012 bill of materials part number ref des qty value tol. voltage power pac kage type jedec type manufacturer description 10tpb330m c04, c08 2 330f 20% 10v smd cap_7343_149 131-4353-00 j1, j4 2 conn tek131-4353-00 2n7002-7-f q1 1 sot23 sot23 31-5329-52rfx j2, j5 2 conn con_bnc_31_5329_52rfx 5002 p1-p8 8 thole mtp500x 575-4 ba1-ba8 8 conn con_ban_575 eevha1e331up cin1, cin4 2 330f 20% 25v smd capae_315x402 grm21br71c475ka73l c1 1 4.7f 10% 16v 805 cap_0805 murata ceramic capacitor grm32er71a476ke15l c01, c03, c05, c07 4 47f 10% 10v 1210 cap_1210 murata ceramic chip capacitor h1045-open c2, c3, c6, c7 4 open 5% open 603 cap_0603 generic multilayer capacitor h1045-00102-16v10 c15, c16 2 1000pf 10% 16v 603 cap_0603 generic multilayer capacitor h1045-00102-50v10 c4, c5, c8, c9 4 1000pf 10% 50v 603 cap_0603 generic multilayer capacitor h1045-open c10, c11, c12, c14 6 open 5% open 603 cap_0603 generic multilayer capacitor h1082-open c02, c06, c09, c010 4 open 10% open 1210 cap_1210 generic ceramic chip capacitor h2505-dnp-dnp-1 r14-r16, r21, rfset 5 dnp 1% dnp 603 res_0603 h2511-00r00-1/16w1 r9, r10, r13, r17, r20 5 0 ? 1% 1/16w 603 res_0603 h2511-01001-1/16w1 r1, r2, r3, r6, r8 4 1k ? 1% 1/16w 603 res_0603 h2511-03321-1/16w1 r11, r12 2 3.32k ? 1% 1/16w 603 res_0603 h2511-16501-1/16w1 r5, r7 2 16.5k ? 1% 1/16w 603 res_0603 h2511-04121-1/16w1 r6, r8 2 4.12k ? 1% 1/16w 603 res_0603 h2511-06650-1/16w1 r4 1 665 ? 1% 1/16w 603 res_0603 h2512-open r18, r19 2 open 0% 1/10w 805 res_0805 isl8225mirz u1 1 qfn qfn26_670x670_isl8225m jumper2_100 jp1-jp7 7 thole jumper-1 ssl-lxa3025igc led1 1 smd led_3x2_5mm tmk325b7226mm-tr cin2, cin3, cin5, cin6 4 22f 20% 25v 12 10 cap_1210 taiyo yuden ceramic chip capacitor
application note 1793 9 intersil corporation reserves the right to make changes in circuit design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1793.1 december 6, 2012 ISL8225MEVAL4Z efficiency curves figure 9. efficiency vs load current (5v in at 500khz) figure 10. efficiency vs load current (12v in ) 50 55 60 65 70 75 80 85 90 95 100 0 2 4 6 8 10 12 14 16 load current (a) efficiency (%) 1v 1.2v 1.5v 1.8v 2.5v 3.3v 50 55 60 65 70 75 80 85 90 95 100 0 2 4 6 8 10 12 14 16 load current (a) efficiency (%) 1.5v at 500khz 1.8v at 500khz 2.5v at 500khz 3.3v at 650khz 5v at 850khz 1.2v at 500khz 1v at 500khz
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